1. Field of the Invention
The present invention relates to a channel-etch thin film transistor, and more particularly to a reverse-stagger channel-etch thin film transistor as a switching device for each pixel of an active matrix liquid crystal display.
All of patents, patent applications, patent publications, scientific articles and the like, which will hereinafter be cited or identified in the present application, will, hereby, be incorporated by references in their entirety in order to describe more fully the state of the art, to which the present invention pertains.
2. Description of the Related Art
In recent years, the importance of development of an active matrix liquid crystal display has been on the increase. The active matrix liquid crystal display has thin film transistors over an insulative substrate, typically a glass substrate. Each of the thin film transistors is provided to control an electric filed to be applied to corresponding one of pixels of the active matrix liquid crystal display. Some types of the thin film transistor have an active layer which comprises amorphous silicon. Such thin film transistor including the amorphous silicon active layer has widely been used due to a relatively low process temperature, for example, about 300° C.
FIG. 1 is a fragmentary plan view of a conventional channel-etch thin film transistor generally used in the active matrix liquid crystal display. FIG. 2 is a fragmentary cross sectional elevation view taken along an X–X′ line of FIG. 1. With reference to FIGS. 1 and 2, a structure of the conventional channel-etch thin film transistor will, hereinafter, be described. A gate electrode 2 of chromium (Cr) is selectively provided on an upper surface of a glass substrate 1. A gate insulation film 3 of silicon nitride (SiNx) extends over the gate electrode 2 and the upper surface of the glass substrate 1, so that the gate electrode 2 is completely buried in the gate insulation film 3. An active layer 4 is selectively provided on an upper surface of the gate insulation film 3, so that the active layer 4 is positioned over the gate electrode 2. The active layer 4 comprises an undoped amorphous silicon. Source and drain layers 5 are selectively provided on top surfaces of the active layer 4. The source and drain layers 5 comprise a phosphorous-doped n+-type amorphous silicon. A source electrode 6 and a drain electrode 7 are further provided over the source and drain layers 5 and the upper surface of the gate insulation film 3 in the vicinity of the active layer 4, so that the source and drain electrodes 6 and 7 are contact directly with the source and drain layers 5 respectively. An inter-layer insulator 8 extends over the upper surface of the gate insulation film 3 as well as over the source and drain electrodes 6 and 7, and also within a gap between the source and drain electrodes 6 and 7 and the source and drain layers 5. The inter-layer insulator 8 comprises silicon nitride (SiNx). The inter-layer insulator 8 has a via hole which reaches a part of an upper surface of a lead portion of the source electrode 6, wherein the lead portion of the source electrode 6 is contact with the upper surface of the gate insulation film 3. A pixel electrode 9 is also selectively provided which extends over the inter-layer insulator 8 and within the via hole, so that a part of the pixel electrode 9 is contact directly with the part of the upper surface of the lead portion of the source electrode 6, whereby the source electrode 6 is electrically connected to the pixel electrode 9. The pixel electrode 9 also extends over an upper surface of the inter-layer insulator 8. The pixel electrode 9 comprises indium tin oxide (ITO).
The liquid crystal display also has an opposite substrate which faces to the above-described substrate 1, which may be referred to as a thin film transistor substrate, wherein an opposite electrode is formed on the opposite substrate, so that the pixel electrode 9 of the thin film transistor substrate 1 is positioned opposite to the opposite electrode of the opposite substrate. Each pair of the pixel electrode 9 and the opposite electrode sandwiches a liquid crystal cell layer for applying an electric field to the liquid crystal cell layer. The opposite substrate also has a back-light unit.
FIGS. 3A through 3G are fragmentary cross sectional elevation views of the conventional channel-etch thin film transistors in sequential steps involved in a conventional fabrication process for fabricating the transistor shown in FIGS. 1 and 2. The fabrication process for fabricating the transistor shown in FIGS. 1 and 2 will further be described with reference to FIGS. 3A through 3I.
With reference to FIG. 3A, a chromium layer is deposited on a clean upper surface of a glass substrate 1 by a sputtering process and then selectively removed, so that a gate electrode 2 of chromium (Cr) is formed on the glass substrate 1.
With reference to FIG. 3B, sequential plasma enhanced chemical vapor deposition processes are taken place, so that a gate insulation film 3 of SiNx is deposited over the gate electrode 2 and the glass substrate 1, and an undoped amorphous silicon layer 4a is deposited on the gate insulation film 3, and further a phosphorous-doped n+-type amorphous silicon layer 5a is deposited on the undoped amorphous silicon layer 4a. 
With reference to FIG. 3C, an anisotropic etching process, for example, a dry etching process is taken place to selectively remove the phosphorous-doped n+-type amorphous silicon layer 5a and the undoped amorphous silicon layer 4a, so that a patterned undoped amorphous silicon layer 4 and a patterned phosphorous-doped n+-type amorphous silicon layer 5 remain over the gate electrode 2.
With reference to FIG. 3D, a further sputtering process is carried out to deposit a chromium layer over the phosphorous-doped n+-type amorphous silicon layer 5 and the upper surface of the gate insulation film 3. Subsequently, the chromium layer is selectively removed by an isotropic etching process, for example, a wet etching process to form source and drain electrodes 6 and 7, respectively. A part of the upper surface of the phosphorous-doped n+-type amorphous silicon layer 5 is exposed through a gap between the source and drain electrodes 6 and 7.
With reference to FIG. 3E, an anisotropic etching process, for example, a dry etching process is carried out by use of the source and drain electrodes 6 and 7 as a mask, so that the phosphorous-doped n+-type amorphous silicon layer 5 under the gap between the source and drain electrodes 6 and 7 is selectively removed, and further the undoped amorphous silicon layer 4 is also selectively removed. The selectively removed phosphorous-doped n+-type amorphous silicon layer 5 act as phosphorous-doped n+-type amorphous silicon source and drain layers 5, while the selectively removed undoped amorphous silicon layer 4 acts as an active layer 4.
With reference to FIG. 3F, a plasma enhanced chemical vapor deposition process is taken place to form an inter-layer insulator 8 of SiNx which extends over the gate insulation film 3 and the source and drain electrodes 6 and 7 as well as within the gap between the source and drain electrodes 6 and 7. The inter-layer insulator 8 is then selectively removed to form a via hole which reaches a part of an upper surface of a lead portion of the source electrode 6, wherein the lead portion extends over the gate insulation film 3. The inter-layer insulator 8 is provided to protect the active layer 4.
With reference to FIG. 3G, a further more sputtering process is carried out to deposit an indium tin oxide layer over the inter-layer insulator 8 and within the via hole, so that a part of the indium tin oxide layer is contact directly with the part of the lead portion of the source electrode 6. The indium tin oxide layer is then selectively removed by an etching process to form a pixel electrode 9 which extends within the via hole and a part of the upper surface of the inter-layer insulator 8.
The following descriptions will focus on issues engaged with the conventional channel-etch thin film transistor.
In recent years, the requirement for increasing the brightness of the liquid crystal display has been on the increase. To comply with this requirement, an intensity of the back-light tends to be increased. In this circumstances, it becomes more important to suppress or reduce a light-off leak current of the thin film transistor. If a light or a photon emitted from the back light is incident into the active layer of the n-channel thin film transistor, then photo-carriers are generated by the photo-electric effect. The light-off leak current is generated with those photo-carriers, particularly holes moving through the channel region and the drain electrode. The light-off leak current causes a pixel potential drop which further causes undesired various phenomenons, for example, a reduction in brightness of the module, a reduction of the contrast, a display spot, and a flicker.
In the conventional channel etch thin film transistor shown in FIGS. 1 and 2, a width of the source and drain electrodes 6 and 7, which are positioned over the active layer 4, is equal to a width of the source and drain electrodes 6 and 7, which are positioned in contact with side walls of the active layer 4, provided that the term “length” is, hereby, defined to be a horizontal size in a first horizontal direction along the X–X′ line of FIG. 1, while the term “width” is defined to be another horizontal size in a second horizontal direction perpendicular to the first horizontal direction or perpendicular to the X–X′ line of FIG. 1. Namely, the entirety of the source electrode 6 has a uniform width, while the drain electrode 7, except for a lead portion extending over the gate insulation layer 3, also has a uniform width which is equal to the width of the source electrode 6. Electron-hole pairs are generated in the active layer 4 by the photo-electric effect. The holes as generated are blocked by the phosphorous-doped n+-type amorphous silicon layer 5, while the holes may move, as the light-off leak current, through a contact region between the side wall of the active layer and the drain electrode 7 and thus into the drain electrode 7. This means that the light-off leak current is increased.
It is disclosed in Japanese laid-open patent publication No. 7-273333 and by Y. E. Chen et al. in Technical Report Of IEICE EID98-216 (March 1999) that in order to reduce such light-off leak current through the side wall of the active layer, insulating films are formed on the side walls of the active layer. The later-mentioned literature further addresses that the insulating films provided on the side walls of the active layer is effective to suppress the conduction of the light-off leak current as generated in the active layer into the source or drain electrode. FIG. 4 is a fragmentary cross sectional elevation view of another conventional channel etch thin film transistor with insulating films on side walls of an active layer for suppressing the light-off leak current as generated in the active layer into the source or drain electrode. The conventional channel etch thin film transistor shown in FIG. 4 may be considered to be modified from the above-described conventional channel etch thin film transistor shown in FIGS. 1 and 2, wherein the conventional channel etch thin film transistor shown in FIG. 4 further includes insulating films 10 on side walls of the active layer 4, so that the side walls of the active layer 4 are separated by the insulating films 10 from the source and drain electrodes 6 and 7. The formation of the insulating films 10 does, however, need an additional high temperature process. FIG. 5 is a fragmentary cross sectional elevation view of the conventional channel etch thin film transistor in the additional step for forming the insulating films on the side walls of the active layer included in the conventional channel etch thin film transistor shown in FIG. 4. The additional step may be carried out following to the step shown in FIG. 3C. The above-mentioned Japanese laid-open patent publication No. 7-273333 discloses that side wall insulating films of SiNx is formed by a plasma enhanced chemical vapor deposition, which may be normally carried out at about 300° C., and subsequent dry etching process. The above-mentioned literature discloses that the side wall insulating films are formed by an anneal at 230° C. for a long time in an oxygen atmosphere. Those relatively high temperature heat treatments, for example, the plasma enhanced chemical vapor deposition and the anneal cause undesired drops of the throughput of the thin film transistors, and thus increase the manufacturing costs thereof.
Japanese patent No. 3223805 discloses a forward-stagger thin film transistor, wherein an amorphous silicon layer, a silicon nitride (SiNx) layer and a chromium (Cr) layer are patterned at the same time when a gate line is patterned. Namely, the amorphous silicon layer, the silicon nitride (SiNx) layer and the chromium (Cr) layer are formed with the same island pattern. This island-pattern allows undesired leakage of current from edge-faces of the islands, whereby the off-leak current is likely to flow from the pixel electrode through an edge portion of the gate line to the drain line. In order to solve this problem, a width of a lead line connecting between the source electrode and the pixel electrode is narrower than a width of the source electrode. This off-leak current is caused by the unique structure that the amorphous silicon layer, the silicon nitride (SiNx) layer and the chromium (Cr) layer have the same pattern, even the side walls of the active layer are not contact with the source and drain electrodes. The last-mentioned Japanese patent is silent on any hole block layer of n+-type. Namely, the mechanism of allowing the off-leak current disclosed in the last-mentioned Japanese patent No. 3223805 is different from the above-described mechanism of allowing the light-off leak current through the contact region between the side wall of the active layer and the source or drain electrode.
Japanese laid-open patent publication No. 61-259565 discloses a reverse-stagger thin film transistor including plural source and drain electrodes over an amorphous silicon layer, wherein those source and drain electrodes have lead portions with a narrower width which are connected commonly to an input signal line and an output signal line, respectively. This Japanese publication No. 61-259565 does not disclose nor teach any hole block layer of n+-type, and also is silent on the reason why the lead portions are narrower than the source and drain electrodes over the amorphous silicon layer. This reverse-stagger thin film transistor is designed to cut off any defective one of the source and drain electrodes from the signal lines, so as to allow the remaining effective source and drain electrodes to operate or perform normally, wherein a short circuit formation between the gate electrode and the source or drain electrode may render the source or drain electrode defective. This Japanese publication No. 61-259565 does not disclose nor teach the light-off leak current.
In the above circumstances, the development of a novel channel etch thin film transistor free from the above problems is desirable.